1. Field of the Invention
This invention pertains to a method of maintaining the structural integrity and thus the strain within at least one heteroepitaxial layer which is bound to an adjacent layer of a different material, forming a heterojunction. Typically such strained heteroepitaxial layers are useful in the fabrication of semiconductor structures such as bipolar transistors and infrared wavelength photodetectors. However, upon subsequent processing of the structures at temperatures higher than the heteroepitaxial layer growth temperature, the strained heteroepitaxial crystal tends to relax, forming dislocations at the heterojunction. The dislocations, combined with the decrease in strain of the heteroepitaxial layer, result in reduced performance of semiconductor devices. The present invention provides a method for processing the semiconductor device at temperatures greater than the strained heteroepitaxial layer growth temperature while maintaining the structural integrity at the heterojunction and the strain within the heteroepitaxial layer, so that the overall performance characteristics of the device are improved.
2. Background of the Invention
Multilayer structures comprising heterojunctions are useful in the fabrication of numerous different electron and optoelectronic devices, one of the most significant electron devices being bipolar transistors. In a typical bipolar transistor, useful charge carriers travel from an emitter region through a base region to a collector region. The bipolar transistor can be of an NPN type, wherein the collector is an N type material, the base is a P type material, and the emitter is an N type material. (P type material refers to a material predominated by positive carriers (holes), whereas N type material refers to a material predominated by negative charge carriers (electrons).) The bipolar transistor can alernatively have the opposite polarity and be of a PNP type, wherein the collector is a P type material, the base in an N type material, and the emitter is a P type material.
It is possible to have the P and N type materials be comprised of one basic crystalline material such as silicon, which is doped to enable each region to function in the desired manner. In such a homojunction transistor, made using one crystalline material such as silicon, the emitter and base doping levels influence the efficiency with which carriers are injected from the emitter. Some charge carriers which are majority carriers in the base portion of the structure and minority carriers in the emitter portion of the structure can be injected from the base to the emitter, degrading the overall efficiency of the transistor. One method of lessening this problem is to use a different crystalline material to form the base region that the crystalline material used to form the emitter region. This results in formation of an interface between one crystalline layer and another which is referred to as a heterojunction. In the case of bipolar transistors, the heterojunction is useful in blocking the injection of one type of carrier from the base to the emitter.
Heterostructures comprising heterojunctions such as Si.sub.1-x Ge.sub.x /Si can be used for both majority-carrier and minority-carrier devices. One of the major proposed applications is for a heterojunction bipolar transistor (HBT), in which the Si.sub.1-x Ge.sub.x layer serves as the base of the bipolar transistor. Recent progress with the strained-layer epitaxy of Si.sub.1-x Ge.sub.x alloys on silicon has generated excitement over the prospect of an HBT which is compatible with existing silicon process technology. The high emitter injection efficiency brought about by the heterojunction in a Si/Si.sub.1-x Ge.sub.x HBT offers a number of advantages. HBTs have been fabricated from layers epitaxially deposited by chemical vapor deposition (CVD) techniques including limited reaction processing (LRP), a technique that relies on rapid changes in substrate temperature to achieve abrupt doping and compositional profiles.
One description of Si/Si.sub.1-x Ge.sub.x Heterojunction Bipolar Transistors Produced by Limited Reaction Processing is presented in a paper by that title authored by C. A. King, et al. which was published in the IEEE Electron Device Letters, Vol. 10, No. 2, February 1989, pp. 52-54. This paper is hereby incorporated by reference, since it provides a good description of the kind of process within which the method of the present invention can be used, and after the disclosure of the present invention, one skilled in the art will be able to provide more flexibility in the production of HBTs. The metastability of strained Si.sub.1-x Ge.sub.x layers on silicon was discussed in this paper by C. A. King, et al. and it was pointed out that special care was taken to ensure that post layer growth processing steps chosen minimized thermal exposure of the base layer.
Another example of the use of SiGe-Base transistors is disclosed in a paper by D. L. Harame, et al., entitled: "High Performance Si and SiGe Base PNP Transistors", Tech. Digest, International Electron Devices Meeting, San Francisco, December 1988, p. 889. Heterojunction PNP transistors with Si.sub.1-x Ge.sub.x -bases were fabricated. Molecular Beam Epitaxy (MBE) was used to deposit both the Si substrate and Si.sub.1-x Ge.sub.x -base layers and the emitter was formed by low temperature epitaxy. Low temperature processing was used in general after the MBE growth of the SiGe-bases.
To gain maximum advantage from the Si.sub.1-x Ge.sub.x base layer of a given thickness, it is necessary to incorporate as much Ge (i.e., have as great an x value) as is consistent with good epitaxial crystal quality of the Si.sub.1-x Ge.sub.x layer. The ideal quality is attained if the Si.sub.1-x Ge.sub.x layer is grown with the lattice planes of the underlying silicon continuing into the Si.sub.1-x Ge.sub.x layer. To the degree that the interface is, in this sense coherent, it will necessarily be found that the Si.sub.1-x Ge.sub.x layer is strained. This strain is known to further enhance the performance of the HBT by increasing the difference between the Si and Si.sub.1-x Ge.sub.x bandgaps. It is therefore desirable to maintain the strained condition during subsequent processing of the structure to the finished devices and circuits.
In the past, such subsequent processing was highly constrained to low temperatures and short time periods at temperature to maintain the conditions of the coherent lattice interface and the strained Si.sub.1-x Ge.sub.x crystal. The processing constraints were based on the knowledge that misfit dislocations may occur across the interface between a substrate and a strained epitaxial film grown on the substrate. For example J. W. Matthews and A. E. Blakeslee, in their paper entitled: "Defects in Epitaxial Multilayers", Journal of Crystal Growth 27 (1974) pp. 118-125, described misfit dislocations in epitaxial multilayers. Multilayers composed of many thin films of GaAs and GaAsP were grown epitaxially on GaAs surfaces. Examination of the multilayers by transmission and scanning electron microscopy revealed that the interfaces between layers were made up of large coherent areas separated by long straight misfit dislocations. These dislocations are the mechanism by which the strain in a crystalline layer relaxes.
For a heteroepitaxial layer of a given composition in a given structure, there is a calculated critical thickness, based on equilibrium theory (which is a function of the bonding and strain energy of bonded atoms in the crystalline lattice structure). When the heteroepitaxial layer thickness is below the critical thickness, the amount of energy required to relax the strain and to create dislocations at the heterojunction (heterointerface) is sufficiently large that the crystalline layer can be processed at high temperatures (exceeding the growth temperature of the crystalline layer) without relaxing the strain or creating dislocations at the heterojunction. When the heteroepitaxial layer thickness exceeds the critical thickness and the layer is processed at high temperatures, misfit dislocations appear with an accompanying strain relaxation and lowering of the energy level in the heteroepitaxial layer. In the cases studied by Matthews and Blakeslee, the layer thicknesses at which misfit dislocations were formed were in satisfactory agreement with the predicted, calculated critical thickness. Once the calculated critical thickness of epitaxial layer growth was exceeded, dislocation generation occurred. The calculated critical thickness depends on the overall structure comprising the heteroepitaxial layer. For example, the calculated critical thickness for a heteroepitaxial Si.sub.1-x Ge.sub.x layer between two thick silicon layers is nearly twice the calculated critical thickness for the same layer on a Silicon substrate by itself.
When the composition of the heteroepitaxial layer is altered, for a given layer thickness, dislocations would be expected to occur as soon as the composition is such that the critical thickness for a heteroepitaxial layer of that composition is exceeded. Subsequent to the work done by Matthews and Blakeslee, Y. Kohama et al. published information about the critical layer thickness of Si.sub.1-x Ge.sub.x /Si heterostructures in a paper entitled: "Determination of the critical layer thickness of Si.sub.1-x Ge.sub.x /Si heterostructures by direct observation of misfit dislocations", in Appl. Phys. Lett. 52(5), Feb. 1, 1988, p.380. The interest in development of Si.sub.1-x Ge.sub.x /Si superlattices was attributed to their potential applications in the fields of infrared photodetectors and field-effect transistors. One of the significant parameters in designing these devices was said to be the critical layer thickness of the Si.sub.1-x Ge.sub.x layers grown on silicon substrates. The critical layer thickness strongly depends on the lattice mismatch between Si.sub.1-x Ge.sub.x and Si. In general, the mismatch is accomodated by elastic strain when the heteroepitaxial layer thickness is less than the critical thickness. When the heteroepitaxial layer thickness is greater than the critical thickness, the lattice mismatch is accommodated by elastic strain and misfit dislocations. The paper presents data related to the critical thickness of Si.sub.1-x Ge.sub.x on a silicon substrate as a function of x, the germanium content of the silicon-germanium crystal.
The following U.S. Patents, which are related to the subject matter of the present invention, provide insight into the kinds of semiconductor devices which employ strained heteroepitaxial layers. In addition, fabrication process limitations are discussed which show the unexpectedness of the discovery which led to the present invention.
U.S. Pat. No. 4,529,455 to Bean et al., dated Jul. 16, 1985, discloses a method for epitaxially growing Ge.sub.x Si.sub.1-x layers on Si utilizing molecular beam epitaxy. The subject matter of this patent is hereby incorporated by reference.
U.S. Pat. No. 4,617,724 to Yokoyama et al., dated Oct. 21, 1986, discusses a process for fabricating heterojunction bipolar transistors with low base resistance. This patent discloses numerous semiconductor structures and discusses the manner in which they function. Several different types of heteroepitaxial layers and heterojunctions are discussed.
U.S. Pat. No. 4,771,013 to Curran, dated Sep. 13, 1988 discloses a process of making a double heterojunction 3-D I.sup.2 L bipolar transistor with a Si/Ge superlattice. Described is a three dimensional, bipolar wafer process for integrating high voltage, high power, analog and digital circuitry. The structure formed by the process includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of &lt;100&gt; crystal orientation, which is etched and with three dimensional transistors formed on it.
U.S. Pat. No. 4,772,924 to Bean et al., dated Sep. 20, 1988, describes a semiconductor device having a strain induced region of altered bandgap. A strained layer superlattice comprising Ge.sub.x Si.sub.1-x layers interleaved with silicon layers provides an excellent photodetector at infrared wavelengths due to the large shift in bandgap caused by the strain in the superlattice.
U.S. Pat. No. 4,529,455 to Bean, referenced above, discusses the growth conditions for molecular beam epitaxy whereby epitaxial thin films of Si.sub.1-x Ge.sub.x may be grown on silicon or germanium substrates for values of x within the range from 0.0 to 1.0. Relatively thick, smooth layers are said to be grown provided the substrate temperature during deposition is within a critical range, the substrate is properly cleaned prior to growth and has a low dislocation density, and the vacuum is a pressure of 5.times.10.sup.-8 Torr or less. The substrate temperature is required to be 550.degree. C. or less for values of x greater than 0.5. For smaller values of x, the growth temperature is permitted to increase, with allowed substrate temperatures being permitted to increase to a value of approximately 650.degree. C. for x less than 0.5. Depending upon the precise value of x, pseudomorphic growth conditions can be maintained for layer thicknesses up to the critical layer thickness, beyond which dislocation-free material cannot be grown.
It is known in the art that it is possible to grow substantially misfit-dislocation-free Si.sub.1-x Ge.sub.x epitaxial films at temperatures near 650.degree. C. for thicknesses more than two times the calculated critical thickness for a single uncapped heteroepitaxial layer. To date there is no generic theory which accurately predicts the relationship between the amount of lattice distortion which may persist at a heterojunction interface between layers of different crystalline composition. Determinations regarding distortion and dislocations have been made empirically for each epitaxial layer/substrate combination, typically as a function of varying composition of the epitaxial layer. It is believed, however, that if the thickness of an epitaxially grown layer upon a substrate is below the critical thickness for that epitaxial layer, the structure can be exposed for extended periods of time to the given temperature, even though that temperature is above the growth or deposition temperature of the epitaxial layer, without the substantial formation of or growth of existing dislocations between the epitaxial layer and the substrate.
Often it is desired to use an epitaxial layer thickness which is greater than the critical thickness to obtain particular device functions or performance levels. However, if single layers of Si.sub.1-x Ge.sub.x are grown on silicon, wherein the germanium fractional content x is greater than or equal to the critical concentration for the layer thickness, upon heating the layered structure above the growth temperature of the Si.sub.1-x Ge.sub.x layer there is rapid relaxation of the strain in the Si.sub.1-x Ge.sub.x layer and the formation of dislocations at the heterojunction, consistent with equilibrium theory. The problem of dislocations between the epitaxially grown layer of one composition and the substrate of a different composition and the relaxation of the strain desired in the epitaxially grown layer have been overcome by using maximum processing temperatures subsequent to the growth of the heteroepitaxial layer which are about the same as the growth temperature of the epitaxial layer. Or, if the subsequent processing temperature is greater than the growth temperature of the heteroepitaxial layer, the temperature used is as low as possible and the time period the temperature is used is less than a minute (typically seconds). Prior to this invention, it has been supposed that all processing above the growth temperature of a heteroepitaxial layer thicker than its calculated critical thickness degrades the layer and thus compromises device performance.
Since it is desired to use higher processing temperatures in subsequent processing steps and to use heteroepitaxial layer thicknesses greater than the critical thicknesses determined for the layer of epitaxially grown crystal on its substrate, it is desired to find a method of maintaining the structural integrity at the heterojunction and the strain in the heteroepitaxial layer during subsequent processing at temperatures greater than the strained heteroepitaxial layer growth temperature.